1. Field of the Invention
The present invention relates to semiconductor devices and methods. In particular, the present invention relates to integrated fuses.
2. Background Art
Integrated fuses, such as polysilicon fuses, are used as programmable elements in a variety of applications. An integrated fuse can be programmed or set to an open or closed state. The open and closed states are also referred to as conditions where the fuse is xe2x80x9cblownxe2x80x9d or xe2x80x9cunblown.xe2x80x9d Typically, an integrated fuse can be programmed to change from an unblown state to a blown state by applying an electric current of sufficient strength to increase the resistance of the fuse. Example applications which use integrated fuses as programmable elements include: programmable read only memory (PROM), static random access memory (SRAM), redundancy implementation in logic devices, die identification, electrically programmable feature selection, and CMOS logic elements. See, Alvai, M., et al., xe2x80x9cA PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process,xe2x80x9d IEDM:855-858 (1997) (referred to herein as the xe2x80x9cAlvai articlexe2x80x9d), and Kalnitsky, A., et al., xe2x80x9cCoSi2 Integrated Fuses on Poly Silicon for Low Voltage 0.18 xcexcm CMOS Applications,xe2x80x9d IEDM:765-768 (1999) (referred to herein as the xe2x80x9cKalnitsky articlexe2x80x9d), both of which are incorporated herein by reference in their entirety.
FIG. 1A is a top view that shows the geometry of a conventional polysilicon fuse 100. FIG. 1B is a cross-sectional view taken along line Axe2x80x94A of FIG. 1A. As shown in FIG. 1A, polysilicon fuse 100 generally includes two contact regions 102, 108 bridged by two transition regions 104, 106 and fuse neck 105. The center of fuse 100 is indicated by the dashed line C. Polysilicon fuse 100 is made up of a heavily doped N type (N+) or heavily doped P type (P+) polysilicon layer 110 with or without silicide layer 120 as shown in FIG. 1B. The unblown fuse resistance of fuse 100 is preferably low in the range of 50 to 100 ohms (xcexa9). Polysilicon fuse 100 becomes electrically open by applying a sufficient amount of energy in a form of current flow so as to blow the fuse. In this example, both silicide layer 120 and polysilicon layer 110 can be blown open as shown in FIG. 1B. The difference in the pre(unblown) and post(blown) fuse resistance values can be made many orders of magnitude such that the blown fuse acts as an open circuit. This open state is shown in FIG. 1B by the presence of a gap within fuse neck 105. This gap may not necessarily occur at the center, however, and may instead start at the contact regions.
In addition, as CMOS device sizes decrease, it is increasingly difficult to blow a polysilicon fuse since the corresponding supply voltage also becomes small. An external power supply is often needed to generate sufficient current flow to create an adequate open fuse state. This is a more costly solution. It is therefore sufficient to blow open only the silicide layer to program the polysilicon fuse. This can be done by the limited internal power supply.
FIGS. 2A and 2B show one conventional polysilicon fuse 200 used as a programmable element as described in the above-referenced Alvai article. As shown in FIG. 2A, polysilicon fuse 200 is formed from a suicide layer 220 on the top of a polysilicon layer 210. Polysilicon layer 210 can be undoped, N+ doped, or P+ doped as shown in FIG. 2A. Silicide layer 220 can include titanium silicide, nickel silicide, platinum silicide, or cobalt silicide. FIG. 2B shows fuse 200 in an open state where the silicide layer has been programmed to create a region 230 where the resistance is made higher because current is now conducted through the higher resistance polysilicon layer 210. The break in the silicide layer may not necessarily occur at the center, however, and may instead start at the contact regions.
Region 230 is created by passing electrical current through silicide layer 220 as part of an agglomeration process. The location where region 230 occurs along fuse 200 is referred to the xe2x80x9cfusing location.xe2x80x9d The fusing location has been reported to be a function of temperature gradient in addition to fuse geometry and pre fuse resistance. See, Alvai, M., et al, IEDM:855-858 (1997).
It is increasingly desirable to achieve a polysilicon fuse having a high mean post fuse resistance with a tight post fuse resistance distribution for a given geometry and pre fuse resistance. Agglomeration needs to reliably start at or very near the center of the fuse neck and proceed toward the contact regions. Further, an improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is needed.
The present invention provides an integrated fuse with regions of different doping located within a fuse neck. During a fusing event, a distribution of temperature peaks occur around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration starts reliably and efficiently within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions.
Further advantages of integrated fuses according to the present invention can include an improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution compared to conventional polysilicon fuses. Integrated fuses of the present invention can be used in variety of applications including but not limited to programmable elements.
According to the present invention, an integrated fuse has a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions each having an end within the fuse neck of the integrated fuse. The first and second regions have first and second types of dopants. These types of dopants are different. In one example, the first type of dopant in the first region comprises an N-type dopant and the second type of dopant in the second region comprises a P-type dopant. In this way, a fusing event is initiated within the fuse neck region when the integrated fuse receives an electrical current stress.
In one embodiment, the first region and second regions are adjacent to one another such that each of the one ends of the first and second regions meet or abut at a common interface. The common interface is located at or near the center of the fuse neck region. In one example implementation, the first type of dopant in the first region is a heavily-doped N-type dopant and the second type of dopant in the second region is a heavily-doped P-type dopant. In another example implementation, the first type of dopant in the first region is a lightly-doped N-type dopant and the second type of dopant in the second region is a lightly-doped P-type dopant.
In another embodiment, the polysilicon layer further includes a third region located at or near the center of the fuse neck region and in between first and second regions of the polysilicon layer. In one implementation, the third region is undoped, while the first type of dopant in the first region is a heavily-doped N-type dopant and the second type of dopant in the second region is a heavily-doped P-type dopant. In another example implementation, the third region is undoped, while the first type of dopant in the first region is a lightly-doped N-type dopant and the second type of dopant in the second region is a lightly-doped P-type dopant.
In another embodiment, the polysilicon layer further includes a third region which is lightly doped with N-type and P-type dopants. First and second regions next to the third region are lightly-doped with respective N-type and P-type dopants.
In another embodiment, the polysilicon layer further includes a third region which is heavily doped with N-type and P-type dopants. First and second regions next to the third region are then heavily-doped with respective N-type and P-type dopants.
Finally, the present invention includes a method for making an integrated fuse. The method includes steps of forming a polysilicon layer that includes first and second regions having different first and second types of dopants, and forming a silicide layer along the polysilicon layer.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.